This invention relates to systems and methods for calibrating offsets in differential amplifiers.
In general, differential amplifiers are configured to amplify the difference of two signals applied to a pair of differential input terminals to produce an output signal. An offset signal often must be applied across the differential input terminals of a differential amplifier in order to reduce the output signal to zero. The source of offset error may arise from the physical design of the differential amplifier or it may arise from process variations. Circuit thresholds, the mismatch of device sizes, and circuit operating conditions are all sources of offset error. Many different analog techniques for calibrating differential amplifier offset error have been proposed. One analog technique involves correct transistor sizing and careful physical layout to minimize the basic offset parameters. Even with an optimal design, however, offset correction by design alone often does not sufficiently control the offset voltage for many differential amplifier applications.
Another analog calibration technique involves the use of a switched capacitor circuit for correcting offset error. A typical switched capacitor circuit uses a high gain differential amplifier with a large offset correction capacitor for sampling and holding offset correction data. Typically, a relatively large offset correction capacitor is used to minimize leakage and decay effects. Fabrication of such a large capacitor, however, involves special integrated circuit process steps and a considerable amount of circuit area. In addition, a very high refresh rate is needed to hold the offset voltage to within typical device specifications (e.g., tens of microvolts).
Other techniques for controlling offset errors in differential amplifiers involve analog controlled offset calibration. In general, these analog techniques typically use special analog circuitry to generate analog control signals. Additional circuits are used to sample and store the analog control signals. Normal circuit leakage currents result in analog control signal data being refreshed frequently. Typically, these analog control techniques are subject to the same sample and hold limitations as switched capacitor techniques.
Still other differential amplifier offset calibration techniques have been proposed.
The invention features a circuit and a method for calibrating offset error in a differential amplifier in an efficient and reliable way. In particular, the invention obtains a final calibrated state for the differential amplifier in accordance with a nonlinear search method that requires significantly fewer test stages to complete than linear search methods. As a result, longer test periods may be used with the invention without adversely affecting the overall length of the calibration process. Because circuit conditions near the calibration point cause internal test signals to switch more slowly from one state to another, lengthening the test period time may allow more time for the internal test signals to reach their final values and, thereby, improve calibration accuracy.
In one aspect, the invention features a calibration circuit that comprises a memory circuit, an output circuit, and a control circuit. The memory circuit is operable to store a set of programming values that are selected from a range of multiple possible sets of programming values. The output circuit is coupled to the memory circuit and is operable to place the differential amplifier in a selected calibrated state by applying to the differential amplifier an output calibration signal that is generated based upon the set of programming values that are stored in the memory circuit. The control circuit is coupled to the memory circuit and is operable to program the memory circuit with a final set of programming values by progressively narrowing the range of possible programming value sets until the final set of programming values is obtained. The range of possible programming value sets is progressively narrowed in test stages in accordance with a nonlinear search. At each test stage, a set of programming values is selected based upon a sensed differential amplifier signal that is generated in response to a test signal that is applied to the differential amplifier in a selected calibrated state.
Embodiments of the invention may include one or more of the following features.
The memory circuit preferably comprises a set of calibration registers. Each calibration register may be gated by a set of global select signals. Each calibration register also may be settable and re-settable.
The output circuit preferably comprises a coarse calibration circuit and a fine calibration circuit. The coarse calibration circuit may comprise a programmable voltage divider circuit. In some embodiments, the coarse calibration circuit is operable to adjust back gate bias voltages applied to one or more transistors in an input stage of the differential amplifier. The fine calibration circuit may comprise a programmable impedance circuit. In some embodiments, the fine calibration circuit is operable to adjust impedance values of one or more transistors in an input stage of the differential amplifier.
The control circuit may be operable to generate a test programming value at a beginning portion of a given test stage and to select a final programming value at an end portion of the given test stage. A selected delay period may separate periods during a given test stage when the test programming value is generated and when the final programming value is selected. In some embodiments, the control circuit progressively narrows the range of possible programming value sets in accordance with a binary search. In these embodiments, the control circuit may progressively narrow the range of possible programming value sets by selecting one value of the final programming value set during each test stage. The values of the final programming value set may be selected in order from most significant bit to least significant bit.
The invention also features a method of calibrating offset error in a differential amplifier.